The predominant computer architecture historically used a single processor to execute sequentially a stream of program instructions retrieved from a central instruction memory over a communication channel, such as a data bus.
In the relatively recent past, “multi-core” processors have become commercially available for so-called personal computers. While such architectures provide two or more processors, they continue to adhere to a general architecture of retrieving program instructions from a central instruction memory over a data bus.
The problem of a generalized and scalable solution to concurrent processing that takes full advantage of all concurrency inherently available in a process remains unsolved.